Embodiments of the disclosed technology relate to a manufacturing method for a low temperature polysilicon thin film transistor (TFT) array substrate.
Low temperature polysilicon (LTPS) technology is initially developed to decrease power consumption of display panels of notebook computers and make the notebook computers become thinner and more light-weighted. The LTPS technology came into trial stage in about 90's of 20th century. The new generation of organic light emitting diode (OLED) display panel developed based on LTPS has also come into practical usage, whose utmost advantage lies in ultra-thinness, light weight, low power consumption and self-illumination. Thus, a brighter color and a clearer image can be presented.
Hereinafter, a manufacturing method for a polysilicon TFT array substrate in the related arts is described by referring to FIGS. 1A-1F.
The procedure of the manufacturing method for the polysilicon TFT array substrate is as follows, and FIGS. 1A-1F are sectional views of the polysilicon TFT array substrate during various manufacturing stages thereof.
Step S101, forming a polysilicon layer.
As shown in FIG. 1A, a buffer layer 12 of a silicon oxide (e.g., SiO2) film is formed on a whole surface of an insulating substrate 11 by a plasma enhanced chemical vapor deposition (PECVD) method. Thereafter, an amorphous silicon (a-Si) layer is formed on the whole surface of the buffer layer 12 by using a PECVD method or the like, after which a polysilicon layer 22 is finally formed by crystallizing the a-Si using an excimer laser annealing (ELA) process, a solid phase crystallizing (SPC) process or the like.
Step S102, forming a gate electrode.
As shown in FIG. 1B, the polysilicon layer is patterned to form a semiconductor layer 13, after which inorganic material SiO2 is deposited on the whole surface of the semiconductor layer 13 to form a gate insulating layer 14. Next, a layer of low resistivity metal is deposited on the gate insulating layer 14 and is patterned to form a gate line with a gate electrode 15a. 
Step S103, implanting dopant ions into the polysilicon layer.
As shown in FIG. 1C, n-type dopant ions of high concentration are doped into the semiconductor layer 13 by using the gate electrode 15a as a mask to form a source region 13a and a drain region 13c. Here, due to the presence of the gate electrode 15a, the dopant ions are not doped into the semiconductor layer between the source region 13a and the drain region 13c, which becomes a channel 13b. 
Step S104, forming an interlayer dielectric layer.
As shown in FIG. 1D, an inorganic material of silicon oxide (e.g., SiO2) is deposited on the whole surface of the substrate formed with the gate electrode 15a by a chemical vapor deposition (CVD) method so as to form an interlayer dielectric layer 16.
Step S105, activating the polysilicon.
The semiconductor layer 13 is activated by performing a rapid thermal annealing (RTA), a laser beam irradiating using an excimer laser, or a furnace annealing on the surface of the semiconductor layer 13.
Step S106, forming source/drain electrodes.
After the activation process is completed in step S105, as shown in FIG. 1E, the gate insulating layer 14 and the interlayer dielectric layer 16 is etched to expose the source and drain regions 13a and 13c so as to form first contact holes 20a and 20b. A dry etching is typically performed to etch the gate insulating layer 14 and the interlayer dielectric layer 16. Next, as shown in FIG. 1F, a layer of low resistivity metal is deposited on the interlayer dielectric layer 16, which is patterned to form a data line perpendicular to the gate line and having a source electrode 17a and a drain electrode 17b. The source and drain electrodes 17a and 17b contact with the source and drain regions 13a and 13b, respectively.
Step S107, hydrogenating the polysilicon.
An inorganic material such as silicon nitride (SiNx) is deposited by using a CVD method on the whole surface of the substrate formed with the source and drain electrodes 17a and 17b to form a passivation layer 18. Further, the substrate is heated up to an endurable temperature range thereof so as to make the hydrogen atoms contained in the passivation layer 18 diffuse into the semiconductor layer.
Step S108, forming a pixel electrode.
The passivation layer 18 is selectively removed to form a second contact hole 40 to expose the drain electrode 17b. Further, a pixel electrode 37 is formed in a pixel region in a manner such that the pixel electrode 37 contacts with the drain electrode 17b through the second contact hole 40.
In the conventional manufacturing method for the polysilicon TFT array substrate, at least six mask processes are needed in total to form the semiconductor layer, the gate line layer, the first contact hole, the data line layer, the second contact hole and the pixel electrode. The increasing number for the mask processes results in a complicated procedure, which increases the processing time and cost accordingly.